Integrated circuit comparators may utilize differential amplifiers to perform a comparison operation on a pair of input signals. As illustrated by FIG. 1A, a conventional integrated circuit comparator 10 may include a pair of differential input transistors N1 and N2, which have gate terminals responsive to a pair of differential analog input signals D+ and D−, and a comparator output circuit. The input transistors N1 and N2 are enabled by driving a clock signal CLK low-to-high to thereby turn on an NMOS pull-down transistor N3. The comparator output circuit is illustrated as including cross-coupled NMOS transistors N4 and N5 and cross-coupled PMOS transistors P1 and P2 having source/drain terminals connected to a pair of differential outputs (OUT+ and OUT−). The differential outputs are equalized at precharged voltage levels (e.g., Vdd) when the clock signal CLK is driven high-to-low to thereby turn on PMOS pull-up transistors P3 and P4 and PMOS equalization transistor P5.
Input resolution, which is an important specification in the comparator 10 of FIG. 1A, is determined by the dc-input offsets and comparator response speed. As will be understood by those skilled in the art, non-zero dc-input offsets are caused by random transistor-transistor variations, which are typically inversely proportional to transistor size (e.g., layout area). Smaller input transistors can be used in the comparator 10 for higher response speed, but typically at a cost of increased dc-input offsets. Thus, there is a trade-off between dc-input offset and response speed.
Random transistor variations in NMOS transistors N1-N4 and PMOS transistors P1-P2 all contribute to increased dc-input offsets, which, as illustrated by the comparator 10′ of FIG. 1B, can be modeled by an input-offset dc voltage source (shown as VOFFSET), which is added in series with an analog input signal (e.g., at negative input terminal D−). To reduce the influence of dc-input offsets, relatively large transistor size can be used, but the use of larger transistors typically increases power consumption and layout area and reduces response speed.